Multi-chip semiconductor apparatus

ABSTRACT

A multi-chip semiconductor apparatus includes a plurality of semiconductor chips stacked and packaged therein, wherein each of the semiconductor chips includes: a through-silicon via (TSV) formed through the semiconductor chip; a probe pad exposed to an outside of the semiconductor chip so as to enable a probing test; a bump pad exposed to the outside of the semiconductor chip and electrically connected to the TSV; and a conductive layer electrically connecting the probe pad and the bump pad inside the semiconductor chip.

CROSS-REFERENCES TO RELATED APPLICATION

The present application is a continuation of U.S. application Ser. No.14/887,233 filed Oct. 19, 2015, which is a divisional of U.S.application Ser. No. 13/720,497 filed on Dec. 19, 2012, now U.S. Pat.No. 9,165,860, issued Oct. 20, 2015, which claims priority under 35U.S.C. § 119(a) to Korean application number 10-2012-0090719 filed onAug. 20, 2012, in the Korean Intellectual Property Office, the entiredisclosures of which are incorporated herein by reference.

BACKGROUND 1. Technical Field

Various embodiments presented herein relate to a semiconductorapparatuses, and more particularly, to a multi-chip semiconductorapparatuses including a plurality of semiconductor chips stacked throughthrough-silicon vias (TSVs).

2. Related Art

Packaging technology for semiconductor apparatuses has continuouslydeveloped to satisfy demands for miniaturization and reliability ofmountings. For example, the demand for miniaturization has acceleratedthe technology development for packages which are close to chip size.The demand for more reliable mountings has driven the importance anddevelopment of packaging technologies capable of improving theefficiency of mounting operations and the mechanical/electricalreliability after mounting.

Furthermore, as high performance electric and electronic products arerequired with miniaturization, various technologies for providing ahigh-capacity semiconductor module have been researched and developed.As a method for providing a high-capacity semiconductor module, highintegration for memory chips may be used. This high integration may berealized by integrating a larger number of cells into a limited space ofa semiconductor chip. However, such high integration for memory chipsrequires a high-level technology and a large amount of development time.For example, a fine critical dimension (CD) may be required. Therefore,improved stack technology may provide benefits in a high integrationenvironment.

SUMMARY

In one embodiment, a multi-chip semiconductor apparatus includes aplurality of semiconductor chips stacked and packaged therein, whereineach of the semiconductor chips includes: a through-silicon via (TSV)formed through the semiconductor chip; a probe pad exposed to an outsideof the semiconductor chip so as to perform a probing test; a bump padexposed to the outside of the semiconductor chip and electricallyconnected to the TSV; and a conductive layer electrically connecting theprobe pad and the bump pad inside the semiconductor chip.

In another embodiment, a multi-chip semiconductor apparatus includes aplurality of semiconductor chips stacked and packaged therein, whereineach of the semiconductor chips includes: a plurality of TSVs formedthrough the semiconductor chip; a probe pad exposed to an outside of thesemiconductor chip so as to perform a probing test; a plurality of bumppads exposed to the outside of the semiconductor chip and electricallyconnected to the respective TSVs; and one or more conductive layerselectrically connecting the probe pad to the respective bump pads insidethe semiconductor chip.

In another embodiment, a multi-chip semiconductor chip includes aplurality of semiconductor chips stacked and packaged therein, whereineach of the semiconductor chip includes: a TSV formed through thesemiconductor chip; a bump pad exposed to an outside of thesemiconductor chip and electrically connected to the TSV through a firstconductive path; an internal circuit formed in the semiconductor chipand electrically connected to the TSV through a second conductive path;and a probe pad exposed to the outside of the semiconductor chip toperform a probing test and electrically connected to the internalcircuit through a third conductive path, each of the first to thirdconductive paths includes a plurality of conductive layers and aplurality of conductive contacts connected between the respectiveconductive layers, and specific conductive layers of the first and thirdconductive paths are electrically connected to each other.

In another embodiment, a multi-chip semiconductor chip apparatusincludes a plurality of semiconductor chips which are electricallyconnected and stacked through a TSV, wherein each of the semiconductorchips includes: a memory cell block; a bump pad electrically connectedto the TSV and configured to transmit and receive information to andfrom the memory cell block; and a probe pad configured to transmit andreceive test information to and from the memory cell block, and during aprobe test after packaging, the probe pad of the semiconductor chip iselectrically connected to the bump pad, and transmits and receives thetest information on the semiconductor chip to and from outside throughthe probe pad of the uppermost semiconductor chip of the semiconductorchips.

Additional alternative embodiments will be apparent to a person ofordinary skill in the art according to the descriptions provided herein.

BRIEF DESCRIPTION OF THE DRAWINGS

Features, aspects, and embodiments are described in conjunction with theattached drawings, in which:

FIG. 1 is a cross-sectional view of a conventional multi-chipsemiconductor apparatus including a plurality of semiconductor chipsstacked through TSVs;

FIG. 2 is a diagram illustrating the structure of a semiconductor chipaccording to one embodiment;

FIG. 3 illustrates one potential embodiment in which a cross-sectionalview of a multi-chip semiconductor apparatus in which a plurality ofsemiconductor chips based on the structure of FIG. 2 are stacked;

FIG. 4 is a diagram illustrating the structure of a semiconductor chipaccording to another embodiment; and

FIG. 5 is a block diagram of a multi-chip semiconductor apparatusaccording to another embodiment.

DETAILED DESCRIPTION

Hereinafter, a multi-chip semiconductor apparatus will be describedbelow with reference to the accompanying drawings through variousembodiments.

A stacked multi-chip semiconductor apparatus has a structure in whichtwo or more semiconductor chips are stacked in one package. As a methodfor stacking a plurality of semiconductor chips in a package, certainstructures may use through-silicon vias (TSVs). In packages using TSVs,holes are formed through the semiconductor chips, and filled with aconductive material to form the TSVs. Through the TSVs, upper and lowersemiconductor chips are electrically connected.

FIG. 1 is a cross-sectional view of a conventional multi-chipsemiconductor apparatus including a plurality of semiconductor chipsstacked through TSVs.

The multi-chip semiconductor 1 illustrated in FIG. 1 includes aplurality of semiconductor chips 10 and 20 stacked over a substrate.

Each of the semiconductor chips 10 and 20 includes a TSV formed byfilling a hole formed therein. For example, the first semiconductor chip10 includes a TSV 11 and bump pads 12 and 13 which are electricallyconnected to both ends of the TSV 11 so as to be exposed to the outside.The bump pads of the semiconductor chips 10 and 20 facing each other maybe connected through a bump 18 such that the TSVs of the respectivesemiconductor chips 10 and 20 are electrically connected to each other.

The TSV 11 of the first semiconductor chip 10 is connected to aninternal circuit 15 through a conductive path 16. That is, variousvoltages/signals used in internal circuits of the semiconductor chips 10and 20 are transmitted to the respective semiconductor chips through theTSVs, and then transmitted to the internal circuits from the TSVsthrough the conductive paths inside the semiconductor chips.

Furthermore, each of the stacked semiconductor chips 10 and 20 includesa probe pad formed thereon, in order to perform a probing test on thesemiconductor chip before the semiconductor chip is stacked andpackaged. The probe pad may include various types of pads to performvarious tests by transmitting and receiving a power supply voltage,various signals, data and the like. For example, the probe pad 14 of thefirst semiconductor chip 10 is electrically connected to the internalcircuit 15 through the conductive path 17.

Each of the conductive path 16 to connect the TSV 11 and the internalcircuit 15 and the conductive path 17 to connect the probe pad 14 to theinternal circuit 15 may include a plurality of conductive layers and aplurality of conductive contacts connected between the respectiveconductive layers. The probe pad 14 may be formed by opening theuppermost conductive layer among the plurality of conductive layers. Theconductive layer may include a metal layer, and the conductive contactmay include a metal contact.

Meanwhile, the probing test for the multi-chip semiconductor apparatus 1could be performed only in a state of mono chips before the respectivechips are stacked and packaged. That is because, since the probe pads ofthe respective chips are not connected through the TSVs, it is difficultto access the probe pads of the respective chips from outside after thepackaging is completed. Currently, there is a demand for a methodcapable of performing a probing test even in a multi-chip semiconductorapparatus having a chip stack structure, which is completely packaged.

FIG. 2 is a diagram illustrating the structure of a semiconductor chip110 according to one embodiment of the present invention. Thesemiconductor chip 110 illustrated in FIG. 2 includes a bump pad 114 anda probe pad 115 which are exposed to the outside of the semiconductorchip 110 and electrically connected through a specific conductive layerM1 inside the semiconductor chip 110.

More specifically, the semiconductor chip 110 includes a TSV (notillustrated.) The TSV may be formed by filling a hole formed therein.The bump pad 114 which is exposed to the outside of the semiconductorchip 110 is electrically connected to the TSV. The semiconductor chip110 includes the probe pad 115 exposed to the outside of thesemiconductor chip, in order to perform a probing test. The probe pad115 and the bump pad 114 are electrically connected through the specificlayer M1 inside the semiconductor chip 110.

Therefore, the probe pad 115 of the semiconductor chip 110 according tothe embodiment illustrated by FIG. 2 may be electrically connected tothe bump pad 114 through the conductive layer Ml, and electricallyconnected to the TSV through the bump pad 114.

FIG. 3 is a cross-sectional view of a multi-chip semiconductor apparatus100 in which a plurality of semiconductor chips based on the structureof FIG. 2 are stacked.

The multi-chip semiconductor apparatus 100 illustrated in FIG. 3includes a plurality of semiconductor chips stacked over a substrate.The embodiment of FIG. 3 illustrates the multi-chip semiconductor 100having first and second semiconductor chips 110 and 120 stacked therein.

The first and second semiconductor chips 110 and 120 each includes a TSVformed by filling a hole formed in the respective chip. In theembodiment illustrated by FIG. 3, the second semiconductor chip 120 hasthe same configuration as the first semiconductor chip 110. Inalternative embodiments, different semiconductor chips may havevariations in the configuration of the chips. The following descriptionsrelated to the embodiment of FIG. 2 will be focused on the configurationof the first semiconductor chip 110.

The first semiconductor chip 110 includes a TSV 111, first and secondbump pads 112 and 114, a probe pad 115, and an internal circuit 116. TheTSV 111 is formed inside the first semiconductor chip 110. The first andsecond bump pads 112 and 114 exposed to the outside of the semiconductorchip 110 are electrically connected to both ends of the TSV 111. In suchan embodiment, the second bump pad 114 formed on the same surface as theprobe pad 115 is electrically connected to the TSV 111 through a firstconductive path 113. The first conductive path 113 includes a pluralityof conductive layers and a plurality of conductive contacts formedbetween the respective conductive layers. In the embodiment of FIG. 3,the conductive layer and the conductive contact may be formed of amaterial to pass a current, for example, a metallic material.

Further, in the embodiment of FIG. 3, the internal circuit 116 isconnected to the TSV 111 through a second conductive path 117. That is,various voltages and/or signals used in the internal circuit 116 aretransmitted to the first semiconductor chip 110 through the TSV 111 fromoutside semiconductor chip 110, and are then transmitted to the internalcircuit 116 from the TSV 111 through the second conductive path 117inside semiconductor chip 110. The second conductive path 117 may alsoinclude a plurality of conductive layers and a plurality of conductivecontacts formed between the respective conductive layers.

The probe pad 115 is exposed to the outside of the semiconductor chip soas to perform a probing operation. The probe pad 115 may include varioustypes of pads such as a power supply pad, a signal input/output pad, anda data input/output pad, in order to perform various tests on thesemiconductor apparatus. The probe pad 115 is electrically connectedthrough the internal circuit 116 and the third conductive pad 118. Thethird conductive path 118 also includes a plurality of conductive layersand a plurality of contacts formed between the respective conductivelayers. In one potential embodiment, the probe pad 115 may be formed byopening the uppermost conductive layer among the plurality of conductivelayers forming the third conductive path 118.

In one potential embodiment, specific conductive layers M1 of the firstand third conductive paths 113 and 118 are electrically connected toeach other. Through the conductive layers M1, the probe pad 115 iselectrically connected to the second bump pad 114, and thus electricallyto the TSV 111.

The specific conductive layer M1 may be formed at any one layer of theplurality of conductive layers of the first and third conductive paths113 and 118, excluding the uppermost conductive layer on which thesecond bump pad 114 and the probe pad 115 are formed. In this way, thesecond bump pad 114 and the probe pad 115 may be electrically connectedwithout having an effect on signal interconnections and powerinterconnections which are arranged around the pads.

Then, as the bump pads of the first and second semiconductor chips 110and 120 facing each other are connected through a bump 119, the TSVs ofthe respective semiconductor chips 110 and 120 may be electricallyconnected to each other.

That is, in the multi-chip semiconductor apparatus according to theembodiment of the present invention, the probe pads formed on therespective semiconductor chips are electrically connected to the TSVs.Accordingly, although packaging is completed after the semiconductorchips are stacked, a probing test for the entire stack of semiconductorchips may be performed by probing the probe pads exposed to the outsideof the stack.

FIG. 4 is a diagram illustrating the structure of a semiconductor chip110_1 according to another embodiment.

The semiconductor chip 110_1 illustrated in FIG. 4 includes a pluralityof bump pads 114_1A and 114_1B and a probe pad 115_1 which are exposedto the outside of the semiconductor chip and electrically connectedthrough specific conductive layers M1_1A and M1_1B, respectively, insidethe semiconductor chip 110_1. The conductive layers M1_1A and M1_1Bconnecting the probe pad 115_1 to the respective bump pads 114_1A and114_1B may be formed at the same layer, or at different layers. FIG. 4illustrates the first bump pad 114_1A and the second bump pad 114_1B,but the present invention is not limited thereto, and alternativeembodiments may include alternative bump pad arrangements. Thesemiconductor chip 110_1 according to an alternative embodiment of thepresent invention may include a structure in which one probe pad such asprobe pad 115_1 is connected to a plurality of bump pads.

More specifically, the semiconductor chip 110_1 includes a plurality ofTSVs (not illustrated) formed by filling holes formed therein. The firstand second bump pads 114_1A and 114_1B exposed to the outside of thesemiconductor chip 100_1 are electrically connected to correspondingTSVs among the plurality of TSVs. The semiconductor chip 110_1 includesthe probe pad 115_1 exposed to the outside to perform a probing test,and the probe pad 115_1 is electrically connected to the first andsecond bump pads 114_1A and 114_1B through the specific conductivelayers M1_1A and M1_1B, respectively, inside the semiconductor chip100_1.

In certain embodiments, multi-chip semiconductor apparatus in which aplurality of semiconductor chips based on the structure of FIG. 4 arestacked has the same structure as illustrated in FIG. 3, except that oneprobe pad is electrically connected to a plurality of bump pads.

In such embodiments, the multi-chip semiconductor apparatus in which aplurality of semiconductor chips based on the structure of FIG. 4 arestacked includes a plurality of bump pads connected to the probe pad,thereby preparing for various defects which may occur during process andstrengthening the connection between the semiconductor chips through theTSVs during a probe test.

FIG. 5 is a block diagram of a multi-chip semiconductor apparatusaccording to another potential embodiment. The embodiment of amulti-chip semiconductor apparatus 1000 illustrated in FIG. 5 has astructure in which a plurality of semiconductor chips are electricallyconnected through TSVs. For example, FIG. 5 illustrates first and secondsemiconductor chips 1100 and 1200 and a TSV 1200 connecting the firstand second semiconductor chips 1100 and 1200. However, the presentinvention is not limited thereto, and in additional alternativeembodiments, a larger number of semiconductor chips may be electricallyconnected and stacked through TSVs. In this embodiment illustrated byFIG. 5, the first semiconductor chip 1100 corresponds to the uppermostsemiconductor chip which is electrically connected to an externalsubstrate.

The first semiconductor chip 1100 includes a memory cell block 1110, abump pad 1130, and a probe pad 1150. The memory cell block 1110 isenabled when a chip select signal CSBO corresponding to the firstsemiconductor chip is activated. The first semiconductor chip 1100 isenabled in response to the first chip select signal CSBO. The memorycell block 1110 is configured to input/output data information accordingto a command applied during a normal operation. The memory cell block1110 is also configured to input/output test information according to acommand applied during a probe test operation.

The bump pad 1130 is electrically connected to the TSV 1200 and servesto transmit and receive signals of the semiconductor chip 1100 to andfrom outside the semiconductor chip 1100. That is, when the first chipselect signal CSBO is activated, the bump pad 1130 receives informationfrom outside semiconductor chip 1100 and applies the receivedinformation to the memory cell block 1110, or receives information fromthe memory cell block 1110 and outputs the received information to anoutput of semiconductor chip 1100.

The probe pad 1150 serves to transmit and output signals of thesemiconductor chip to and from outside of semiconductor chip 1100 duringa probe test. That is, when the first chip select signal CSBO isactivated during the probe test mode, the probe pad 1150 receives testinformation from outside semiconductor chip 1100 and applies thereceived test information to the memory cell block 1110, or receivesinformation from the memory cell block 1110 and outputs the receivedinformation to outside of semiconductor chip 1100.

The second semiconductor chip 1300 also includes a memory cell block1310, a bump pad 1330, and a probe pad 1350.

The memory cell block 1310 is enabled when a chip select signal CSB1corresponding to the second semiconductor chip is activated, like thefirst semiconductor chip 1100. The second semiconductor chip 1300 isenabled in response to the second chip select signal 1300. The memorycell block 1310 inputs/outputs data information according to a commandapplied during a normal operation, and input/outputs test informationaccording to a command applied during a probe test operation.

The bump pad 1330 is electrically connected to the TSV 1200, and servesto transmit and receive signals of the semiconductor chip to and fromoutside semiconductor chip 1300. In one potential embodiment, the bumppad 1330 of the second semiconductor chip 1300 is electrically connectedto the bump pad 1130 of the first semiconductor chip 1100 positionedover the second semiconductor chip 1300 through the TSV 1200, andtransmits and receives signals to and from outside through the bump pad1130 of the first semiconductor chip 1100. That is, when the second chipselect signal CSB1 is activated, the bump pad 1330 receives informationfrom outside and applies the received information to the memory cellblock 1310, or receives information from the memory cell block 1310 andoutputs the received information to outside.

The probe pad 1350 may serve to transmit and receive signals of thesemiconductor chip to and from outside during a probe test. In a statewhere a plurality of semiconductor chips are packaged, it may bedifficult to perform a test by directly probing a probe pad, except forthe uppermost semiconductor chip which exposes a probe pad. According tovarious embodiments, however, the probe pad 1350 is electricallyconnected to the bump pad 1300. Therefore, a probe test for the secondsemiconductor chip 1300 positioned inside may be performed through theTSV 1200. That is, by probing the probe pad 1150 of the firstsemiconductor chip 1100 positioned at the uppermost part, it is possibleto perform a probe test on another semiconductor chip positioned inside,for example, the second semiconductor chip 1300. Specifically, when thesecond chip select signal CSB1 is activated during a probe test mode,test information is transmitted to or received from the probe pad 1350.Then, the test information is transmitted to or received from outsidethe chip through the probe pad 1150 of the first semiconductor chip 1100positioned at the uppermost part through the TSV 1200.

While certain embodiments have been described above, it will beunderstood to those skilled in the art that the embodiments describedare by way of example only. Accordingly, the multi-chip semiconductorapparatus described herein should not be limited based on the describedembodiments. Rather, the multi-chip semiconductor apparatus describedherein should only be limited in light of the claims that follow whentaken in conjunction with the above description and accompanyingdrawings.

What is claimed is:
 1. A method of testing a multi-chip package having afirst semiconductor chip with an externally accessible probe pad and asecond semiconductor chip arranged under the first semiconductor chip,the method comprising: receiving a first test information via the probepad of the first semiconductor chip, the first test information beingprovided to a first memory cell block of the first semiconductor chip;transmitting a second test information from the first memory cell blockof the first semiconductor chip via the probe pad of the firstsemiconductor chip; receiving a third test information via the probepad, the bump pad of the first semiconductor chip, the first TSV of thefirst semiconductor chip, a second TSV of the second semiconductor chipand a bump pad, a probe pad of the second semiconductor chip, the thirdtest information being provided to a second memory cell block of thesecond semiconductor chip; and transmitting a fourth test informationfrom the second memory cell block of the second semiconductor chip viathe probe pad, the bump pad of the second semiconductor chip, the secondTSV of the second semiconductor chip, the first TSV of the firstsemiconductor chip and the bump pad, the probe pad of the firstsemiconductor chip.
 2. The method of claim 1, wherein the second memorycell block of in the second semiconductor chip is enabled in response toa corresponding chip select signal prior to the transmitting andreceiving test information to and from the second memory cell block. 3.A method of testing a multi-chip package having a plurality ofsemiconductor chips, each of the semiconductor chips including athrough-silicon via (TSV) formed through the semiconductor chip, a probepad formed at least one of a first surface and a second surface of thesemiconductor chip, an internal circuit formed in the semiconductorchip, bump pads electrically connected to both ends of the TSV, and aplurality of connecting portions electrically connected between the TSVand the probe pad, between the probe pad and the internal circuit,between the internal circuit and the TSV, and between the TSV and atleast one of the bump pads, the semiconductor chips being electricallyconnected by a bump which positioned between the bump pads, the methodcomprising: packaging the plurality of the semiconductor chips which arestacked, to be exposed a selected probe pad; and serving a signal by theexposed probe pad thereby performing a probe test, wherein the signal istransmitted to other semiconductor chips through the connectingportions, the TSV and the bump.
 4. The method according to claim 3,wherein each of the semiconductor chips includes a memory cell blockreceiving a chip select signal.
 5. The method according to claim 4,wherein the probe test is performed on the semiconductor chip includingthe memory cell block receiving an enabled chip select signal.
 6. Themethod according to claim 4, wherein the signal serving the exposedprobe pad passes through the memory cell block receiving the enabledchip select signal and does not pass through the memory cell blockreceiving a disabled chip select signal.
 7. The method according toclaim 3, wherein the selected probe is pad is positioned at an uppermostsemiconductor chip of the plurality of the semiconductor chips.